1. Field of the Invention
The present disclosure relates to semiconductor device structures and, more particularly, to a layout of gate structures and contact structures of semiconductor device structures.
2. Description of the Related Art
In modern electronic equipment, integrated circuits (ICs) experience a vast applicability in a continuously spreading range of applications. In particular, the demand for increasing mobility of electronic devices at high performance and low energy consumption drives developments to more and more compact devices having features with sizes significantly smaller than 1 μm, the more so as current semiconductor technologies are apt of producing structures with dimensions in the magnitude of 100 nm or less. With ICs representing a set of electronic circuit elements integrated on a semiconductor material, normally silicon, ICs may be made much smaller than any discreet circuit composed of separate independent circuit components. Indeed, the majority of present-day ICs are implemented by using a plurality of circuit elements, such as field effect transistors (FETs), also called metal oxide semiconductor field effect transistors or MOSFETs, occasionally also simply referred to as MOS transistors, and passive elements, such as resistors, e.g., diffusion resistors, and capacitors, integrated on a semiconductor substrate within a given surface area. Typical present-day ICs involve millions of single circuit elements formed on a semiconductor substrate.
In the design and fabrication of advanced ICs, an IC is represented by means of so-called IC layouts indicating planar geometric shapes which correspond to the pattern of metal, oxide or semiconductor layers that make up the components of the integrated circuit. Standard processes for fabricating advanced ICs are based on well-known and well-understood interactions of many chemical, thermal and photographic variables which are carefully controlled and on which the behavior of the final IC largely depends. Important variables herein are given by positions and interconnections of the geometric shapes of the various layers used to build components of ICs.
Usually, when designing an IC, the components intended for making up a microchip are placed and connected in an IC layout such that the final chip meets certain criteria, typically: performance, size, density and manufacturability. On the basis of the data as provided by an IC layout, semiconductor foundries generate photomasks to be used in the various photolithography processes employed in current process flows.
It is typically checked whether the layout satisfies a series of recommended parameters (called design rules) before sending the layout of ICs to semiconductor foundries. The design rules are provided by semiconductor manufacturers as a series of parameters and enable the designer to verify the correctness of a mask set. For example, a set of design rules specifies certain geometric and connectivity restrictions to provide sufficient margins accounting for variability in semiconductor manufacturing processes. In this way, it is ensured that most of the parts work correctly.
Driven by Moore's Law, there is an ongoing challenge in the semiconductor industry to reduce the area consumed by layouts based on cost and performance aspects. As a consequence, technology nodes of present ICs are constantly shrinking as much as possible. With shrinking technology nodes, the physical effects become more and more important, such as, for example, mechanical stress, contact etch behavior and the like. Additionally, the downscaling of semiconductor devices causes electrical fields with certain geometric dimensions. With the dimensions of advanced semiconductor devices being smaller than 65 nm, the electrical behavior of transistor devices cannot only be treated as being solely dependent on the width and length dimension of a transistor. For example, upon reaching the 28 nm technology node, the electrical behavior of transistors was observed to depend on design rules defining a great number of geometric dimensions and shapes of the various features in complex semiconductor devices, as will be described below with regard to FIG. 1.
FIG. 1 shows in a top view a semiconductor device structure having a plurality of active regions 10, 20, 30, 40 and 50. In each of the active regions 10, 20, 30, 40 and 50, gates overlying the active regions are formed, e.g., gate 12 and dummy gates 14 over the active region 10, gate 22 and dummy gates 24 over the active region 20, dummy gate 44 over the active region 40, and dummy gate 54 over the active region 50. Typically, dummy gates are formed to reduce production tolerances.
By means of the following design rules (depending on the technology node), a semiconductor foundry allows designers to design only the layout pattern as seen in the top view, while thicknesses of layers are fixed by the semiconductor foundry. The design rules will be explained relative to the active region 10. For example, the geometry and shape of the active region and the gates are set on the basis of the following parameters, as illustrated in FIG. 1: W, L, OSEa defining a separation between adjacent active regions parallel to the length dimension L, OSEb setting a spacing between adjacent active regions parallel to the W dimension, PSE setting a spacing between two neighboring gate structures 12, 14, within an active region, CPP (“contacted poly pitch”) setting a repetitive spacing between two neighboring gates including a length of the gates and dummy gates parallel to the L dimension, LOD (SA) defining a minimum spacing between an active gate structure 12 and a boundary of the active region 10 to the left side (parallel to the L dimension), LOD (SB) defining an according spacing between an active gate 12 and a boundary of the active region 10 to the right side (parallel to the L dimension), and the PC overlap setting margins and overlap of the gate structures 12, 14 relative to the active region 10. Length dimensions of the gate structures 12 and the dummy gate structures 14 are indicated in FIG. 1 via Lgate and Ldummy, respectively. The aforementioned design rules are not limiting and further design rules may be imposed by the semiconductor foundry to define the geometry and shape of source/drain contacts C1, C2 and gate contacts CG.
From the above description, it is therefore desirable to provide a semiconductor device structure allowing small layout standard cell footprints in VLSI (“very large scale integration”) layouts at 28 nm and below, without giving raise to area penalty.